Nuvoton EN MA35D1 Linux BSP&nbsp NewRS User manual

Brand: Nuvoton

Model: EN MA35D1 Linux BSP&nbsp NewRS

Type: User manual

MA35D1 Linux

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NuMicro® Family

Arm® Cortex®-A35-based Microcontroller

MA35D1 Linux

User Manual

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of NuMicro®

microcontroller and

microprocessor based system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com

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Table of Contents  
OVERVIEW ...................................................................................................... 5 
LINUX KERNEL CONFIGURATION ................................................................ 6 
DEVICE DRIVERS ........................................................................................... 7 
1 System ............................................................................................................................ 7 
1.1 System Controller ............................................................................................................. 7 
1.2 CPU .................................................................................................................................... 7 
1.3 Clock Controller ................................................................................................................ 7 
1.4 Interrupt Controller ........................................................................................................... 8 
1.5 Memory .............................................................................................................................. 8 
1.6 Power management ......................................................................................................... 9 
1.7 Hardware Semaphore ...................................................................................................... 9 
1.8 Wormhole .......................................................................................................................... 9 
1.9 TEE ................................................................................................................................... 10 
1.10 remoteproc ...................................................................................................................... 11 
1.11 rpmsg ............................................................................................................................... 12 
1.12 PDMA ............................................................................................................................... 12 
2 Timers ............................................................................................................................ 13 
2.1 Generic Timer.................................................................................................................. 13 
2.2 Timer ................................................................................................................................ 13 
2.3 RTC .................................................................................................................................. 15 
2.4 Enhanced PWM .............................................................................................................. 15 
2.5 Watchdog Timer (WDT) ................................................................................................. 16 
2.6 Window Watchdog Timer (WWDT) .............................................................................. 17 
3 I/O .................................................................................................................................. 17 
3.1 pinctrl & GPIO ................................................................................................................. 17 
3.2 Keypad Interface (KPI) .................................................................................................. 20 
3.3 EBI .................................................................................................................................... 22 
4 Connectivity .................................................................................................................. 25 
4.1 UART ................................................................................................................................ 25 
4.2 SPI .................................................................................................................................... 26 
4.3 I2C ..................................................................................................................................... 29 
4.4 MCAN ............................................................................................................................... 30 
5 Networking .................................................................................................................... 31 
5.1 GMAC............................................................................................................................... 31 
5.2 Wi-Fi ................................................................................................................................. 33 
6 USB ............................................................................................................................... 33 
6.1 USB Host ......................................................................................................................... 33 
6.2 USB Device ..................................................................................................................... 35 
7 Storage .......................................................................................................................... 36 

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7.1 SDHC ............................................................................................................................... 36 
7.2 NAND ............................................................................................................................... 37 
8 Multimedia .................................................................................................................... 39 
8.1 CMOS Sensor Interface ................................................................................................ 39 
8.2 Display Interface ............................................................................................................. 41 
8.3 2D Graphic Engine ......................................................................................................... 46 
8.4 H.264 and JPEG Decoder............................................................................................. 46 
8.5 I2S ..................................................................................................................................... 48 
9 Cryptographic ............................................................................................................... 49 
9.1 Crypto Accelerator .......................................................................................................... 49 
9.2 TRNG ............................................................................................................................... 51 
9.3 Key Store ......................................................................................................................... 51 
10 Analog ..................................................................................................................... 51 
10.1 ADC .................................................................................................................................. 52 
10.2 Enhanced ADC ............................................................................................................... 53 
10.3 Temperature Sensor ...................................................................................................... 54 
FILE SYSTEMS .............................................................................................. 56 
1 EXT2/3/4 ....................................................................................................................... 56 
2 FAT ................................................................................................................................. 56 
2.1 exFAT ............................................................................................................................... 56 
3 UBIFS ............................................................................................................................ 57 
4 JFFS2 ............................................................................................................................ 58 
5 initramfs ......................................................................................................................... 59 
6 NFS ................................................................................................................................ 59 
7 sysfs............................................................................................................................... 60 
8 debugfs ......................................................................................................................... 60 
BUILDING LINUX BSP .................................................................................. 61 
1 Yocto .............................................................................................................................. 61 
1.1 Update TF-A .................................................................................................................... 61 
1.2 Update OP-TEE .............................................................................................................. 61 
1.3 Update u-Boot ................................................................................................................. 62 
1.4 Update Linux Kernel ...................................................................................................... 63 
2 Buildroot ........................................................................................................................ 63 
3 Reducing Boot Time .................................................................................................... 65 
USER APPLICATIONS .................................................................................. 66 
1 alsa-utils ........................................................................................................................ 66 
2 ethtool ............................................................................................................................ 66 

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6.3 GStreamer .................................................................................................................... 66

6.4 mtd-utils ......................................................................................................................... 67

6.5 Qt ................................................................................................................................... 68

6.6 wpa_supplicant and wpa_cli ...................................................................................... 68

7 REVISION HISTORY ..................................................................................... 70

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1 OVERVIEW

The NuMicro® MA35D1 series microprocessor is based on dual 64/32-bit Arm® Cortex®-A35 cores at

Armv8-A architecture running up to 800 MHz and a Arm® Cortex®-M4 core at ARMv7-M architecture

running up to 180 MHz. The MA35D1 series includes built-in 128 KB mask ROM and supports booting

from USB, SD/eMMC, NAND and SPI Flash (SPI-NOR/SPI-NAND), up to 384 (256 + 128) KB on-chip

SRAM and 16-bit DDR2/DDR3L SDRAM interface running up to 533 MHz. The MA35D1 series is

equipped with AES, SHA, ECC, RSA cryptographic engine and a true random number generator

(TRNG) for secure boot and high security features. The MA35D1 series is also equipped with a LCD

Display controller, 2D Graphic Engine, H.264 decoder for HMI display applications. The MA35D1

series supports Gigabit Ethernet MAC, USB 2.0 high-speed host, device controller and CMOS sensor

for advanced connectivity applications and CAN-FD. The MA35D1 series also supports plenty of

peripherals including UART, ISO-7816 interfaces, Quad-SPI, SPI, I2C, I2S, EPWM, 12-bit SAR ADC,

32-bit timers, WDT (Watchdog Timer), WWDT( Window Watchdog Timer), 32.768 kHz oscillator and

RTC (Real Time Clock), for comprehensive product application scenarios.

This document introduces the Linux kernel features that are related with MA35D1. Chapter 2 to

chapter 4 covers the Linux configuration and device tree modification. Chapter 5 list the commands for

building and cleaning kernel. And Chapter 6 covers the usage of some frequent used application

including the ALSA command line utility, network interface configuration tool ethtool, media streaming

library GStreamer, Qt GUI system, and MTD device tool mtd-utils.

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2 LINUX KERNEL CONFIGURATION

There is a default configuration for the MA35D1 series provided by Nuvoton. Before modifying any

configuration of kernel, it is recommended to load the default configuration of kernel first. User can

type “make ma35d1_defconfig” command with ARCH set as “arm64” to do so. Sometimes if system

cannot boot up, user can load the default configuration to recovery kernel to safe status.

$ make ARCH=arm64 ma35d1_defconfig

Sometimes fine-tune kernel configuration, for example to enable some features that are not enabled

by default, or to remove unused feature to speed up booting time. Linux kernel provides an interface to

enter configuration menu by typing “make menuconfig” command with ARCH set as “arm64”.

$ make ARCH=arm64 menuconfig

This is a multi-layer menu in configuration system. In the current page, user can press arrow keys to

control the layer of configuration system. Select kernel function by pressing “up” or “down” key and

select menu function in the bottom of page by pressing “left” or “right” key. To enter the next layer of

configuration page, user can press “enter” key.

There are five functions at the bottom of menu page. User can disable or enable kernel function by

pressing space key when cursor stays at “Select”. The symbol in front of the selection function “[ ]”

stands for this function is disabled, “[*]” stands for this function is enabled and “[M]” stands for this

function is built as module and can be loaded dynamically.

Menu page can be returned to upper layer by pressing space key when cursor stays at “Exit” at the

bottom of menu page. If it’s at the top layer of configuration system, system will inform user if wants to

save the configuration and exit.

The help screen will show when cursor is at “Help” by pressing space key. To save current

configuration or load old configuration, use can press space key when cursor is at “Save” or “Load” at

the bottom of menu page.

The kernel configuration file will be named “.config” and be saved in the Linux source tree directory.

In buildroot environment, use the following command to enter Linux kernel menuconfig

$ make linux-menuconfig

In Yocto environment, use the following command to enter Linux kernel menuconfig

$ bitbake linux-ma35d1 -c menuconfig

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3 DEVICE DRIVERS

To support MA35D1, the kernel platform must enable MA35D1 series.

Platform Selection --->

[*] Nuvoton MA35D1 SOC Family

3.1 System

3.1.1 System Controller

A system control node should be added in the device tree allowing other driver to get the base

address of system control registers. Here shows the system control node of MA35D1 in the device

tree.

sys: system-management@40460000 {

compatible = "nuvoton,ma35d1-sys", "syscon", "simple-mfd";

reg = <0x0 0x40460000 0x0 0x200>;

};

3.1.2 CPU

The “cpus” node describes the CPU and L2 cache attribute in MA35D1. Some models contain duo

Cortex-A35 core while others contain single core. Foe the system using single core parts, a device

tree without “cpu1” should be used so Linux kernel knows there is only one CPU core in the system.

cpus {

#address-cells = <2>;

#size-cells = <0>;

...

cpu1: cpu@1 {

device_type = "cpu";

compatible = "arm,cortex-a35";

reg = <0x0 0x1>;

enable-method = "psci";

next-level-cache = <&L2_0>;

};

...

};

3.1.3 Clock Controller

Clock controller is a function block that controls the on/off switch of peripheral clock, peripheral clock

source, and divider. Here are the driver source codes of MA35D1 clock controller.

 drivers/clk/nuvoton/clk-ma35d1.c

 drivers/clk/nuvoton/clk-ma35d1-pll.c

 drivers/clk/nuvoton/clkdivider-ma35d1.c

The clock controller driver above is always built in kernel image if the architecture is select as MA35D1

in kernel configuration. A function node in the device tree describes the clock controller’s feature.

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clk: clock-controller@40460200 {

“compatible” and “reg” has to set as following example, otherwise the driver cannot function properly.

compatible = "nuvoton,ma35d1-clk", "syscon", "simple-mfd";

reg = <0x00000000 0x40460200 0x0 0x100>;

#clock-cells = <1>;

There are 5 PLLs in MA35D1, following entries defines their default clock rate and clock switch.

assigned-clocks = <&clk CAPLL>,

<&clk DDRPLL>, <&clk APLL>,

<&clk EPLL>, <&clk VPLL>;

assigned-clock-rates =<1000000000>,

<266000000>, <200000000>,

<500000000>, <102000000>;

MA35D1 PLL supports 3 different modes. Mode 0 stands for normal PLL operations. Mode 1 stands

for the specific clock output frequency, such like 147.456 MHz. Mode 2 stands for EMI consideration.

clock-pll-mode = <0>, <1>, <0>, <0>, <0>;

nuvoton,sys = <&sys>;

};

3.1.4 Interrupt Controller

MA35D1 contains the ARM GICv2 interrupt controller to dispatch interrupt events in the system. The

driver that supports GICv2 is:

 drivers/irqchip/irq-gic.c

The GIC device node defines the base address of GIC registers where “compatible” should set to

“arm,gic-400”. The base address of GIC distributor, CPI interface, Virtual interface control blocks, and

Virtual CPU interfaces are 0x50801000, 0x50802000, 0x50804000, and 0x50806000 respectively.

gic: interrupt-controller@50800000 {

compatible = "arm,gic-400";

#interrupt-cells = <3>;

interrupt-parent = <&gic>;

interrupt-controller;

reg = <0x0 0x50801000 0 0x1000>, /* GICD */

<0x0 0x50802000 0 0x2000>, /* GICC */

<0x0 0x50804000 0 0x2000>, /* GICH */

<0x0 0x50806000 0 0x2000>; /* GICV */

This entry defines the VGIC maintenance and should keep as is.

interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |

IRQ_TYPE_LEVEL_HIGH)>;

};

3.1.5 Memory

The memory node described the total DDR size listed below. The “device_type” should set to

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“memory”, and the “reg” attribute defines the total memory size and base address. The base address

for DDR is 0x80000000 for MA35D1 and the size may be 2GB, 1GB, 512MB, 256MB, or 128MB. Here

is an example setting for a 256 MB memory system.

memory@80000000 {

device_type = "memory";

reg = <0x00000000 0x80000000 0 0x10000000>;

};

3.1.6 Power management

User can control MA35D1 enter power down mode by setting /sys/power/state. To send MA35D1

enter power down mode, write “mem” into /sys/power/state.

$ echo mem > /sys/power/state

3.1.7 Hardware Semaphore

MA35D1 provides 8 hardware semaphores, which can be used to synchronize between different

processors using different semaphore keys. The driver for MA35D1 hardware semaphore is:

 drivers/hwspinlock/ ma35d1_hwsem.c

Please follow the setting below to enable wormhole support in Linux kernel.

Device Drivers --->

[*] Hardware Spinlock drivers --->

<*> MA35D1 Hardware Semaphore support

Here describes the hardware semaphore description element in MA35D1 device tree.

The base address of wormhole controller, set to 40380000.

hwsem: hwspinlock@40380000 {

“compatible” must set to “nuvoton,ma35d1-hwsem”.

compatible = "nuvoton,ma35d1-hwsem";

“reg” defines the base address and size of hardware semaphore control register.

reg = <0x0 0x40380000 0x0 0x1000>;

Set “okay” to enable hardware semaphore, otherwise set to “disable”.

status = "okay";

};

3.1.8 Wormhole

MA35D1 Wormhole Controller driver supports 4 bi-direction channels (#0~#3) for data transfer with fix

message size 4 words, 4 general interrupt channels (#4~#7) for sending signal only, and 1 status

channel (#8) for detecting Cortex-M4 status power status change and reset event. The driver for

MA35D1 wormhole control is:

 drivers/mailbox/ma35d1-wormhole.c

MA35D1 wormhole function is always enabled in MA35D1 Linux kernel.

Device Drivers --->

-*- Mailbox Hardware Support --->

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-*- MA35D1 Wormhole

Here describes the wormhole device node in MA35D1 device tree.

The base address of wormhole controller, set to 403A0000.

wormhole: mailbox@403A0000 {

“compatible” must set to “nuvoton,ma35d1-wormhole”.

compatible = "nuvoton,ma35d1-wormhole";

“reg” defines the base address and size of wormhole controller register.

reg = <0x0 0x403A0000 0x0 0x1000>;

“interrupts” defines the interrupt used by wormhole controller.

interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

“wakeup-source” is an optional attribute to enable system wakeup from wormhole interrupt event.

wakeup-source;

“#mbox-cells” defines the number of cells required for the mailbox specifier. Must be 1

#mbox-cells = <1>;

Set “okay” to enable wormhole, otherwise set to “disable”.

status = "okay";

};

Here is an example of mailbox client. “mboxes” is the standard property to specify a mailbox channel.

that declares an entry to allocate wormhole channel 1. In this example the mailbox client register

channel 1 for Tx and Rx.

wormhole_test: wormhole_test{

mboxes = <&wormhole 1>;

}

3.1.9 TEE

The MA35D1 series employs the trusted OS OP-TEE running in Cortex-A35 trust zone. The Linux

TEE driver plays the role of a communication bridge between OP-TEE and Linux world. MA35D1

TRNG, Crypto, and Key Store can work in secure or non-secure mode. While TRNG, Crypto, and Key

Store are working in secure mode, the drivers turn into OP-TEE client drivers, which register to Linux

TEE subsystem to communicate with the corresponding PTA (Pseudo Trusted Application) in OP-

TEE.

The Linux TEE subsystem is in folder:

 drivers/tee

And the OP-TEE device driver is in folder:

 drivers/tee/optee

TRNG, Crypto, and Key Store OP-TEE client drivers are in files:

 drivers/char/hw_random/ma35d1-trng.c

 drivers/crypto/nuvoton

 drivers/misc/ma35d1-ks.c

Please follow the setting below to enable OP-TEE support in Linux kernel.

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Device Drivers --->

[*] Trusted Execution Environment support

TEE drivers --->

<*> OP-TEE

Below is the device tree node setting of OP-TEE.

firmware {

optee {

“compatible” should be set to "linaro,optee-tz", which can load the OP-TEE driver.

compatible = "linaro,optee-tz";

OP-TEE driver support both HVC and SMC call to communicate with OP-TEE. MA35D1 always use

SMC call. “method” should be set to “smc”.

method = "smc";

};

3.1.10 remoteproc

The remoteproc framework allows different platforms/architectures to control (power on, load firmware,

power off) those remote processors while abstracting the hardware differences, so the entire driver

doesn't need to be duplicated. The driver for MA35D1 remote processor boot is:

 drivers/remoteproc/ma35d1_rproc.c

Please follow the setting below to enable remoteproc support in Linux kernel.

Device Drivers --->

Remoteproc drivers --->

[*] Support for Remote Processor subsystem

<*> MA35D1 remoteproc support

Below is the device tree node setting of remoteproc.

“compatible” should be set to " nuvoton, ma35d1-rproc ", which can load the remoteproc driver.

rproc {

compatible = "nuvoton, ma35d1-rproc";

status = "okay";

};

User can load and start the remote processor firmware through the SysFS interface:

 Add new path: The firmware components are stored in the file system, by default in

the /lib/firmware/ folder. Optionally another location can be set. In this case the remoteproc

framework parses this new path in priority. Below the command for adding a new path for

firmware parsing:

$ echo -n <firmware_path> > /sys/module/firmware_class/parameters/path

 Set firmware name: If the firmware elf filename differs from the default one (rproc-%s-fw), set the

name with the following command: (replace X with remoteproc instance number: 0 by default).

$ echo -n <firmware_name.elf> > /sys/class/remoteproc/remoteprocX/firmware

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 Start firmware: To start the firmware, use the following command:

$ echo start > /sys/class/remoteproc/remoteprocX/state

 Stop firmware: To stop the firmware, use the following command:

$ echo stop > /sys/class/remoteproc/remoteprocX/state

3.1.11 rpmsg

MA35D1 rpmsg driver provides support for shared memory found on Nuvoton MA35D1 SoC. The

driver for MA35D1 rpmsg is:

 drivers/rpmsg/ma35d1_rpmsg.c

Please follow the setting below to enable rpmsg support in Linux kernel.

Device Drivers --->

Rpmsg drivers --->

-*- RPMSG device interface

<*> MA35D1 Shared Memory Driver

Below is the device tree node setting of rpmsg.

“compatible” should be set to " nuvoton, ma35d1-rpmsg ", which can load the rpmsg driver.

rpmsg {

compatible = "nuvoton,ma35d1-rpmsg";

“share-mem-addr” define share memory address and should be 0x2401ff00.

share-mem-addr = <0x2401ff00>;

“mboxes” register rpmsg to MA35D1 Wormhole channel 2 for TX and RX.

mboxes = <&wormhole 2>;

“tx-smem-size” define tx share memory size and should be 128.

tx-smem-size = <128>;

“rx-smem-size” define rx share memory size and should be 128.

rx-smem-size = <128>;

};

3.1.12 PDMA

The MA35D1 contains four PDMA controllers and each controller supports 10 channels. So there are

40 PDMA channels in total. The driver for MA35D1 PDMA is:

 drivers/dma /ma35d1-dma.c.

Following kernel options has to be enable in order to support PDMA function.

Device Drivers --->

[*] DMA Engine support --->

<*> MA35D1 DMA support

Each PDMA controller has its own device node in device tree, below is the example for PDMA0.

pdma0: pdma@40080000 {

“compatible” must set to “nuvoton,ma35d1-pdma”.

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compatible = "nuvoton,ma35d1-pdma";

Base address of PDMA0 is 0x40080000. It is 0x40090000, 0x400A0000, and 0x400B0000 for PDMA1

~ 3 respectively.

reg = <0x0 0x40080000 0x0 0x2000>;

Interrupt number of PDMA0 is 18, and increase by 1 for each PDMA.

interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;

PDMA have 10 channels, dma-requests is number of DMA request lines supported, up to 32.

clocks = <&clk PDMA_GATE>;

#dma-cells = <1>;

#dma-channels = <10>;

#dma-requests = <32>;

Set “status” to “enable” to enable PDMA, otherwise set to “disable”.

status = "okay";

};

3.2 Timers

3.2.1 Generic Timer

The generic timer of MA35D1 provides a standardized timer framework for Arm v8 cores, and is used

by Linux kernel as the backend of clock source and clock event timers. They are compiled by default

for ARM64 architecture and the source file is:

 drivers/clocksource/arm_arch_timer.c

Below is the device node of generic timer in device tree and should keep as is for MA35D1. The

“clock-frequency” is set to the 12MHz because generic timer’s clock source is fix to HXT / 2, where

HXT is 24MHz for MA35D1 systems.

timer {

compatible = "arm,armv8-timer";

interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |

IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */

<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |

IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */

<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |

IRQ_TYPE_LEVEL_LOW)>, /* Virtual */

<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |

IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */

clock-frequency = <12000000>;

interrupt-parent = <&gic>;

};

3.2.2 Timer

Except the Cortex-A35 builds in generic timer, the MA35D1 also consists of other timers that can

operates in toggle output mode to generate a 50% duty ratio output, event counting mode to calculate

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input event count, free counting mode and trigger counting mode to calculate external event

frequency, or to use as a trigger source to wake up system periodically. The driver of such timer is

locate in:

 drivers/misc/ma35d1-timer.c

This driver can be enabled with following kernel configuration.

Device Drivers --->

Misc devices --->

<*> Nuvoton MA35D1 TIMER support

Here describes the time related node in MA35D1 device tree.

The base address of timer is 0x40500000 + 0x10000 * x / 2 where x = 0, 2, 4…10, and 0x40500100 +

0x10000 * (x – 1) / 2 where x = 1, 3, 5…11.

timer0: timer0@40500000 {

“compatible” should set to “nuvoton,ma35d1-timer”, and register base address set to the address just

mentioned.

compatible = "nuvoton,ma35d1-timer";

reg = <0x0 0x40500000 0x0 0x100>;

Interrupt number for timer 0~11 are 47, 48, 49, 50, 81, 82, 106, 107, 108, 109, 127 and 128

respectively.

interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;

The “port-number” should be equal to the timer number.

port-number = <0>;

Following entries assign the clock enable gate and clock selection mux. Should be “tmrx_gate” and

“tmrx_mux”, where x is the timer number.

nuvoton,clk = <&clk>;

clock-enable = "tmr0_gate";

clock-names = "tmr0_mux";

status configure the timer status after system boot up, could be ether “okay” or “disabled”.

status = "disabled";

};

There are several ioctl commands defined in uapi/misc/ma35d1_timer.h that user application can

issue these ioctl commands to control timer to operate in different modes.

 TMR_IOC_CLKLXT

Switch timer peripheral clock source to LXT.

 TMR_IOC_CLKHXT

Switch timer peripheral clock source to HXT.

 TMR_IOC_STOP

Stop timer.

 TMR_IOC_PERIODIC

Start timer to operate in periodic mode with specified frequency.

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 TMR_IOC_PERIODIC_FOR_WKUP

Start timer to operate in periodic mode and enable timer timeout event to wake up

system.

 TMR_IOC_TOGGLE

Start timer to operate in toggle output mode with specified frequency.

 TMR_IOC_EVENT_COUNTING

Start timer to operate in event counting mode. User application can read the event

counter with read() function.

 TMR_IOC_FREE_COUNTING

Start timer to operate in free counting mode. User can read the calculated duration with

the read() function.

 TMR_IOC_TRIGGER_COUNTING

Start timer to operate in trigger counting mode. User can read the calculated duration with

the read() function.

3.2.3 RTC

The MA35D1 contains RTC to measure current time and trigger alarm event on designated time. The

driver that supports MA35D1 RTC is:

 drivers/rtc/ma35d1_rtc.c

Bellow list the kernel options to enable RTC support:

Device Drivers --->

Real Time Clock --->

[*] Enable MA35D1 RTC driver

Here is the device node describes RTC in device tree.

rtc: rtc@40410000 {

“compatible” must set to “nuvoton,ma35d1-rtc”.

compatible = "nuvoton,ma35d1-rtc";

“reg” defines the base address and size of RTC register map. The base address is 0x40410000 for

RTC. And the RTC interrupt number is 5.

“clocks” defines the clock switch of RTC.

reg = <0x0 0x40410000 0x0 0x10000>;

interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;

clocks = <&clk RTC_GATE>;

status = "okay";

};

3.2.4 Enhanced PWM

The MA35D1 supports EPWM to generate PWM output that can be used for industrial control. The

driver source code of EPWM is:

 drivers/pwm/pwm-ma35d1.c

The following lists the kernel options to enable PWM support.

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Device Drivers --->

[*] Pulse-Width Modulation (PWM) Support --->

<*> Nuvoton MA35D1 EPWM support

Here is the device node describes EPWM in device tree.

epwm0: epwm0@40580000 {

“compatible” should set to “nuvoton,ma35d1-epwm”.

compatible = "nuvoton,ma35d1-epwm";

The register base of EPWM0 is 0x40580000. The base address of EPWM1 and EPWM2 are

0x40590000 and 0x405A0000.

reg = <0x0 0x40580000 0x0 0x10000>;

“clocks” defines the clock switch of EPWM.

clocks = <&clk EPWM0_GATE>;

status = "disabled";

};

3.2.5 Watchdog Timer (WDT)

The MA35D1 contains 3 watchdog timers, where WDT1 is the only one that can be configured to be

accessible from Cortex-A35 non-secure world. In other words, WDT1 is the watchdog timer should be

control by Linux system. The driver of MA35D1 WDT is:

 drivers/watchdog/ma35d1_wdt.c

To support WDT, following kernel options has to be enabled.

Device Drivers --->

[*] Watchdog Timer Support --->

[*] Update boot-enabled watchdog until userspace takes over

(1) Timeout value for opening watchdog device

<*> Nuvoton MA35D1 Watchdog Timer

Below is the device node for WDT1. “compatible” attribute should set to “nuvoton,ma35d1-wdt”.

wdt1: wdt@40440000 {

compatible = "nuvoton,ma35d1-wdt";

reg = <0x0 0x40440000 0x0 0x100>;

Interrupt number of WDT1 is 43.

interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;

The next three entries are used to define the clock control attribute of WDT1 and should keep as is.

nuvoton,clk = <&clk>;

clock-enable = "wdt1_gate";

clock-names = "wdt1_mux";

If the system uses WDT interrupt as a wake up source, “wakeup-enable” should set to <1>, and set to

<0> otherwise.

wakeup-enable = <0>;

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Set “status” to “okay” to enable WDT1, and “disabled” to disable WDT1.

status = "disabled";

};

3.2.6 Window Watchdog Timer (WWDT)

Unlike watchdog timer that software can be reset it whenever convenient before timeout event

triggered, window watchdog timer defines a specific timing window and reset the system immediately

if it receives a reset command outside of the window, or receives a timeout event. So the application

which is responsible to reset WWDT has to issue WDIOC_GETTIMELEFT ioctl command to check

remaining time until window opens and only issue the WDIOC_KEEPALIVE command after remaining

window time dropped to 0. Another major difference is that WWDT pause itself when all Cortex-A35

cores are in idle or power down mode whichever the peripheral clock source is selected. So the

system can stay in idle or power down mode without setting a timer to wake up the system to reset

WWDT periodically. And please note that except a system reset event, WWDT1 cannot be stopped

once WWDT is enabled. The driver source code of MA35D1 WWDT is:

 drivers/watchdog/ma35d1_wwdt.c

To include WWDT driver support, following kernel options have to be enabled.

Device Drivers --->

[*] Watchdog Timer Support --->

<*> Nuvoton MA35D1 Window Watchdog Timer

MA35D1 contains 3 WWDTs, where WWDT1 is reserved to be used by Linux kernel. Below is the

device node for WWDT1. “compatible” attribute should set to “nuvoton,ma35d1-wwdt”. Register base

address is 0x40440100.

wwdt1: wwdt@40440100 {

compatible = "nuvoton,ma35d1-wwdt";

reg = <0x0 0x40440100 0x0 0x100>;

Interrupt number of WWDT1 is 44.

interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;

The next three entries are used to define the clock control attribute of WWDT1 and should keep as is.

nuvoton,clk = <&clk>;

clock-enable = "wdt1_gate";

clock-names = "wwdt1_mux";

Set “status” to “okay” to enable WWDT1, and “disabled” to disable WWDT1.

status = "disabled";

};

3.3 I/O

3.3.1 pinctrl & GPIO

pinctrl and GPIO driver are used to configure the multi-function pin settings and control the GPIO pin

attributes. The driver source codes are:

 drivers/pinctrl/nuvoton/pinctrl-nvt.c

 drivers/pinctrl/nuvoton/pinctrl-ma35d1.c

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To enable pinctrl and GPIO support in Linux, please enable following options in configuration

interface.

Device Drivers --->

-*- Pin controllers --->

-*- MA35D1 pinctrl driver

-*- GPIO Support --->

(512) Maximum number of GPIOs for fast path

[*] /sys/class/gpio/... (sysfs interface)

Below is a reference of the pinctrl and GPIO node defined in device tree for MA35D1. The

“compatible” should set to “nuvoton,ma35d1-pinctrl”, and “nuvoton,sys” provides the base address of

system control registers to pinctrl driver.

pinctrl: pinctrl {

compatible = "nuvoton,ma35d1-pinctrl";

nuvoton,sys = <&sys>;

#address-cells and #size-cells should keep as it.

#address-cells = <2>;

#size-cells = <2>;

status = "okay";

The MA35D1 has 14 GPIO ports in total, from A ~ N. Each port has to declare its register base,

interrupt number, and clock port in device tree. Below is the declaration example for port A. There are

two register bases, 0x40040000 and 0x40040800. The former is for port control and the latter is for

individual pint control. The port A interrupt number 14, and clock gate is “gpa_gate”.

The register base address of GPIO ports are adjacent to each other, and contains 0x40 bytes. The

interrupt number for port B ~ N are 15 ~ 17, 73 ~ 78, and 102 ~ 105.

gpioa: gpioa@40040000 {

reg = <0x0 0x40040000 0 0x40>,

<0x0 0x40040800 0 0x40>;

interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

clocks = <&clk GPA_GATE>;

gpio-controller;

#gpio-cells = <2>;

interrupt-controller;

#interrupt-cells = <2>;

};

...

“pcfg_default” defines a pin configuration with default slew rate, Schmitt trigger disabled and pull

up/down disabled.

pcfg_default: pcfg-default {

Set “slew-rate” to 0 for normal slew rate and 1 to high slew rate.

slew-rate = <0>;

Add “input-schmitt-disable” to disable Schmitt trigger and “input-schmitt-enable” to enable Schmitt

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trigger.

input-schmitt-disable;

Add “bias-disable” to disable internal pull up and pull down. Add “bias-pull-up” to enable internal pull

up, add “bias-pull-down” to enable internal pull down.

bias-disable;

“power-source” could be either 3300 or 1800 depending on the I/O voltage is 3.3V or 1.8V.

power-source = <3300>;

“drive-strength” controls the output driving strength, valid range is between 0~7, the higher the

stringer. And 0 is the default setting.

drive-strength = <0>;

};

Here is an example for GMAC pins on MA35D1 board.

pcfg_emac_1_8V: pcfg-pcfg_emac_1_8V {

slew-rate = <0>;

input-schmitt-enable;

bias-disable;

power-source = <1800>;

drive-strength = <1>;

}

};

There are a total of 14 ports of GPIO in MA35D1, namely PA ~ PN. In MA35D1’s GPIO driver, it

reserves 16 pin number for each no matter how many physical pins exist in the port. So gpio0 ~

gpio15 maps to PA0 ~ PA15. And gpio16~gpio31 maps to PB0 ~ PB15 and so on.

Below is an example to set PC1 to output high using shell commands through sysfs. Since each port

reserved 16 spaces, PC1 is GPIO number 16 * 2 +1 = 33. So the commands below controls GPIO33.

$ echo 33 > /sys/class/gpio/export

$ echo out > /sys/class/gpio/gpio33/direction

$ echo 1 > /sys/class/gpio/gpio33/value

You can use gpio-leds and gpio-keys dirvers to control gpio pins

 drivers/leds/leds-gpio.c

The kernel options to enable gpio-leds support are:

Device Drivers --->

[*] LED Support --->

<*> LED Support for GPIO connected LEDs

Here is a device tree example of a leds-gpio. Set gpioa2 to low and gpiod2 to high.

gpio_leds {

compatible = "gpio-leds";

status = "okay";

led0 {

label = "GPA2 LED";

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gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;

};

led1 {

label = "GPD2 LED";

gpios = <&gpiod 2 GPIO_ACTIVE_HIGH>;

};

 drivers/input/keyboards/gpio_keys.c

The kernel options to enable GPIO buttons support are:

Device Drivers --->

Input device support --->

<*> Generic input layer (needed for keyboard, mouse, ...)

<*> Event interface

[*] Keyboards --->

<*> GPIO Buttons

Here is a device tree example of a GPIO keys. Set GPA1 to active high and GPD1 to active low.

gpio_keys {

compatible = "gpio-keys";

status = "okay";

autorepeat;

botton0 {

label = "GPA1 Key Down";

linux,code = <116>;

gpios = <&gpioa 1 GPIO_ACTIVE_HIGH>;

wakeup-source;

};

button1{

label ="GPD1 Key Up";

linux,code = <117>;

gpios = <&gpiod 1 GPIO_ACTIVE_LOW>;

wakeup-source;

};

3.3.2 Keypad Interface (KPI)

The MA35D1 supports matrix keypad interface sized from 2(row) x 1(column) up to 6(row) x 8(column)

with programmable de-bounce time. The driver of MA35D1 keypad is:

 drivers/input/keyboards/ma35d1_keypad.c

The kernel options to enable MA35D1 keypad support are:

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Nuvoton EN MA35D1 Linux BSP&nbsp NewRS User manual

Nuvoton EN MA35D1 Linux BSP&nbsp NewRS User manual

Nuvoton EN MA35D1 Linux BSP&nbsp NewRS User manual

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